Saving power for mobile devices such as laptops, handheld devices and other devices are known which, for example, reduce overall system power consumption by reducing a memory clock that is controlled to run at a lower frequency such as when a laptop system is disconnected from an AC supply and operates in a battery mode. The memory clock may be provided, for example, by a phase lock loop circuit located on a graphics controller chip or any other suitable chip and provides clock and strobe pulses and other information to a memory chip, such as a DDRRAM, ROM or any other suitable memory. Memory clock frequency is typically reduced in connection with determining that a memory bandwidth requirement is at a low level, for frame buffer memories.
However, reducing a clock by reprogramming a phase lock loop circuit can typically require the use of a delay lock loop on a memory chip as well as a corresponding delay lock loop circuit on a graphics controller, or other suitable integrated circuit. For example, the delay lock loop on the graphics controller may be used to delay a STROBE signal when used for example in a double data rate RAM or any other suitable memory to compensate for delays on a circuit board or on other substrates. For example, controlling of such memory clock frequencies typically requires the need to wait for the DLLs to lock. There are typically DLLs on both the source chip that provides the memory clock such as a graphics controller, and in the memory element such as the RAM chip, ROM chip or any other suitable memory chip.
However, when system memory also contains the frame buffer used by graphics controller and the system memory clock is changed, the system runs the risk of locking up completely since the host processor also accesses the system memory.
In one example, a known method includes stopping memory access clients from making memory requests prior to changing the frequency of the memory clock that is supplied to the memory chip. Moreover, such power reduction systems typically are carried out by a host processor under the control of a software driver and the software driver may be too slow to program all of the registers necessary to change the memory clock to allow the DLLs to relock within one frame or refresh cycle. As a result, a user can see a flash on the screen.
Another problem can arise where a processor, such as a graphics controller, or other suitable processor is integrated in a memory bridge circuit, such as a north bridge circuit. In such systems, the system memory also contains the frame buffer used by the graphics controller to output pixel information for display on a display device. Prior methods would stop all memory requests and can result in a killed system since system memory requests are also stopped. As such, when client memory access are stopped, data being written for example may be corrupted causing the entire system to potentially lock up.
It is also known for memory chips to have a soft refresh mode which effectively shuts down the chip so that it need not employ an external memory clock but still retains and saves data. However, such a self refresh mode is not typically used in prior art clock frequency control based power reduction circuits.
Accordingly, a need exists to overcome one or more of the above deficiencies.